1. Field of the Invention
The present invention relates to the design of semiconductor chips. More specifically, the present invention relates to a method and an apparatus for generating equivalent waveforms used in timing analysis and in signal integrity analysis for an integrated circuit design.
2. Related Art
Timing and signal integrity are ever increasingly important issues in integrated circuit design, particularly due to the increase in clock frequency, chip size and the decrease in device geometry and desired power consumption. Timing analysis, such as static timing analysis, is used to verify, and aid in the correction of chip timing problems. In general, static timing analysis compares the worst case timing of all possible paths between an input signal and an output signal to a preset criterion. Timing analysis is typically performed at the transistor or cell level using libraries of information, such as delay and slew, based on simple input waveforms for the transistor or cell.
One of the most common sources of timing and signal integrity errors is crosstalk, which is mainly due to the capacitive coupling of adjacent conductors. Crosstalk generally causes a distortion in the waveform of an input signal, which may result in incorrect logic transition, e.g., a gate may switch at an incorrect time, or delay variations on a signal line. The delay variation may propagate downstream and cause a timing violation in other parts of the circuit. Accordingly, it is important to account for crosstalk in timing analysis by accurately modeling the actual distorted waveform with an equivalent waveform that represents the actual distorted waveform.